An SRAM cell array is a common test structure used in yield ramp. This is due to its ability to localize defects to within a given cell.
Unfortunately, the fabrication of the SRAM cell requires a large number of processing steps. For example, an isolation layer is formed, gates are patterned, junctions are patterned and formed, etc. Although most of the yield loss occurs as a result of the backend steps, the front-end steps must also be completed to make functioning SRAM blocks. Thus, all the backend processing, typically including three layers of metal and the passivation layer for the pads, must also be done before the devices can be tested electrically. Such extensive number of fabrication steps before yield loss may be determined is very time consuming.
An additional problem with the SRAM test structure is that even though the electrical defect is localized to a certain cell, it does not localize the failing layer. Failure analysis of the defective cell requires layer by layer deprocessing, which is also time consuming and expensive.
Accordingly, there is a need for improved test structures and methods for detecting defects. Additionally, there is a need for improved test structures that can be fabricated with a minimal photolithography masking steps or layers and in which defects can be localized to specific layers.